	// verilator_coverage annotation
	module hazard_detection(
 000013	    input  wire      ex_mem_read,
 026347	    input  wire[4:0] id_rs1,
 013233	    input  wire[4:0] id_rs2,
 000083	    input  wire[4:0] ex_rd,
 006569	    input  wire      br_ctrl,
%000009	    output wire      load_stall,
 006569	    output wire      flush
	);
	assign load_stall = ex_mem_read && (ex_rd == id_rs1 || ex_rd == id_rs2);
	assign flush      = br_ctrl;
	
	
	endmodule
	
